The NCP Retina: An Imager, a Halftoner and a Micro-Grained Array Processor on the Same Chip

@inproceedings{bzd_esscirc92,
    author  = "Bernard, T. and Zavidovique, B. and Devos, F.",
    title   = "The {NCP} Retina: An Imager, a Halftoner and a Micro-Grained Array Processor on the Same Chip",
  booktitle = "Proc. European Solid State Circuits Conf.",
    address = "Copenhagen, Denmark",
    pages   = "159-162",
    month   = sep,
    year    = 1992
}

Abstract
An electronic retina is a device which intimately associates an imager with processing facilities on a monolithic circuit. Yet, except for simple environnements and applications, analog hardware will not suffice to process and compact the raw image flow from the photosensitive array. To solve this output problem, an on-chip array of bare boolean processors with halftoning facilities might be used, providing versatility from programmability. By setting the pixel memory size to three bits, we have demonstrated both the technological practicality and the computational efficiency of this "boolean retina" concept. Using semi-static shifting structures and tricky circuitry, a minimal retina boolean processor can be built with less than 30 transistors and controlled by as few as 5 global clock signals. The successful design, integration and test of such a 65x76 boolean retina on a 50 mm2 CMOS 2µm circuit are presented.

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